Methods for Wafer Scale Processing of Needle Array Devices

ABSTRACT

Methods of fabricating needle arrays on a wafer scale include etching a wafer of columns and needles and coating the same with an electrically insulating material and exposing electrically conductive tips. This process can benefit from using a slow spin speed to distribute resist material across the wafer before etching and using a carrier wafer to support singulated arrays to allow full coverage of upper array surfaces with electrically insulating materials. These processes allow for efficient high volume production of high count microelectrode arrays with a high repeatability and accuracy.

RELATED APPLICATION

This application claims the benefit of U.S. Patent Application No. 61/052,509, filed May 12, 2008 which is incorporated herein by reference. This application is also related to U.S. patent application Ser. No. 11/807,763, filed May 29, 2007 which is incorporated herein by this reference.

BACKGROUND OF THE INVENTION

The potential for implanting electronic devices into patients with direct interface to the neural system is vast. Systems which may enable paraplegics to regain control of their bladder or limbs, provide vision for the blind, or restore vocal cord function are all under development, and promising initial results have been obtained in some experiments.

A key component of some implantable systems is a needle array to enable interfacing of the electronics with a neuron or directly into brain tissue. For example, U.S. Pat. No. 5,215,088 to Normann et al. discloses a three-dimensional electrode device which can be used as a neural or cortical implant. The device of Normann, also known as the Utah Electrode Array (UEA), can be used to provide a neural interface to electronic equipment for sensing and/or stimulation. Alternative approaches for fabricating similar devices are known, but require a large number of masking steps which also slows down production and increases cost of manufacture.

SUMMARY OF THE INVENTION

A general embodiment of the present invention sets forth a method for wafer-scale fabrication of needle arrays. The method can include mechanically modifying the upper surface of a primary wafer to produce a plurality of vertically-extending columns. The next steps involve etching the primary wafer to produce a plurality of needles from the plurality of vertically-extending columns. Tips of the plurality of needles can be coated with an electrically conductive coating. A retainer wafer can be secured to the lower surface of the wafer at based ends of the plurality of needles before separating or singulating the wafer into a plurality of individual needle arrays while leaving the retainer wafer intact. The individual needle arrays can then be encapsulated with an electrically insulative coating so that edges of the arrays are covered by the electrically insulative coating. The tips of the plurality of needles can also be de-encapsulated to expose a desired amount of tip area.

Another general embodiment of the present invention sets forth a structure for processing a needle array, comprising a plurality of columns extending vertically from a substrate and situated on the periphery of the substrate, as well as a plurality of needles circumscribed by the plurality of columns. The plurality of columns defines a well in which the plurality of needles is situated, and wherein the well has a depth sufficient to contain a quantity of material that can submerge the plurality of needles, without the need for an additional container.

There has thus been outlined, rather broadly, the more important features of the invention so that the detailed description thereof that follows may be better understood, and so that the present contribution to the art may be better appreciated. Other features of the present invention will become clearer from the following detailed description of the invention, taken with the accompanying drawings and claims, or may be learned by the practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional features and advantages of the invention will be apparent from the detailed description which follows, taken in conjunction with the accompanying drawings, which together illustrate, by way of example, features of the invention; and, wherein:

FIG. 1 is a perspective illustration of a wafer that has been mechanically modified to produce a plurality of vertically extending columns in accordance with an embodiment of the present invention.

FIG. 2A is a wafer after wafer-scale etching in accordance with an embodiment of the present invention.

FIG. 2B is a wafer after resist coating in accordance with an embodiment of the present invention.

FIG. 2C is a wafer after UV exposure and developing of resist to expose tips in accordance with an embodiment of the present invention.

FIG. 2D is a wafer after metallization over exposed tips and resist in accordance with an embodiment of the present invention.

FIG. 2E is a wafer after lift-off of portions of metallization leaving metalized tips in accordance with an embodiment of the present invention.

FIG. 3 is an SEM micrograph of a UEA of metallized tips using a process in accordance with an embodiment of the present invention.

FIG. 4 is a plot showing the relationship between spinning speed of resist application and needle tip exposure in accordance with an embodiment of the present invention.

FIG. 5A through 5M is a schematic diagrams of a process flow for wafer scale processing of an electrode array in accordance with another embodiment of the present invention.

FIG. 6 is an SEM micrograph of tip de-insulation using foil masking having a relatively high non-uniformity.

FIG. 7 is an SEM micrograph showing de-insulated tips in accordance with an embodiment of the present invention having a high tip length uniformity.

FIG. 8A through 8G are schematic diagrams of a process flow for wafer scale production incorporating irregular backside geometry such as wireless features in accordance with another embodiment of the present invention.

Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In describing embodiments of the present invention, the following terminology will be used.

The singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a needle” includes reference to one or more of such needles and “etching” includes one or more of such steps.

As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary.

Concentrations, amounts, and other numerical data may be expressed or presented herein in a range format. It is to be understood that such a range format is used merely for convenience and brevity and thus should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. As an illustration, a numerical range of “50-250 micrometers” should be interpreted to include not only the explicitly recited values of about 50 micrometers and 250 micrometers, but also include individual values and sub-ranges within the indicated range. Thus, included in this numerical range are individual values such as 60, 70, and 80 micrometers, and sub-ranges such as from 50-100 micrometers, from 100-200, and from 100-250 micrometers, etc. This same principle applies to ranges reciting only one numerical value and should apply regardless of the breadth of the range or the characteristics being described.

As used herein, the term “about” means that dimensions, sizes, formulations, parameters, shapes and other quantities and characteristics are not and need not be exact, but may be approximated and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like and other factors known to those of skill. Further, unless otherwise stated, the term “about” shall expressly include “exactly,” consistent with the discussion above regarding ranges and numerical data.

As used herein with respect to an identified property or circumstance, “substantially” refers to a degree of deviation that is sufficiently small so as to not measurably detract from the identified property or circumstance. The exact degree of deviation allowable may in some cases depend on the specific context.

In the present disclosure, the term “preferably” or “preferred” is non-exclusive where it is intended to mean “preferably, but not limited to.” Any steps recited in any method or process claims may be executed in any order and are not limited to the order presented in the claims. Means-plus-function or step-plus-function limitations will only be employed where for a specific claim limitation all of the following conditions are present in that limitation: a) “means for” or “step for” is expressly recited; and b) a corresponding function is expressly recited. The structure, material or acts that support the means-plus function are expressly recited in the description herein. Accordingly, the scope of the invention should be determined solely by the appended claims and their legal equivalents, rather than by the descriptions and examples given herein.

As mentioned above, needle arrays, such as the Utah Electrode Array (UEA) have been the subject of experimental use. Accordingly, fabrication of the UEA to date has been one array at a time. This process is time consuming, and has yielded less consistency in results than desirable, especially for clinical use. The present invention provides methods for fabrication of microelectrode arrays that are more amenable to mass production while providing more consistent array characteristics.

The method includes mechanically modifying the wafer to produce a plurality of vertically extending columns. Mechanical modification of the wafer can be accomplished using any suitable technique such as, but not limited to, sawing, ablation, or any other suitable material removal technique. The wafer can be sawed or cut using a dicing saw. Alternate techniques for cutting the trenches may include deep reactive ion etching, electro-discharge machining (EDM), and the like. For example, FIG. 1 illustrates a mechanical modification of a wafer 10. The wafer 10 can be sawed on a front side 12 along a first plurality of lines 14 to produce a plurality of vertically-extending columns 16. The sawing can produce saw kerfs 18 which extend into the wafer. For example, the wafer may be about 2 mm thick, and the saw kerfs extend about 1.5 mm into the wafer, although other dimensions can also be readily produced.

As can be seen in FIG. 1, depending on the spacing of the saw cuts, the size of the columns produced can be varied. By forming evenly spaced saw cuts in one direction, and then turning the wafer 90 degrees with respect to the cutting path and making a second set of evenly spaced saw cuts, a plurality of square columns can be produced. For example, the columns can be about 250 micrometers on each side, spaced about 400 micrometers apart. Spacing can be varied to produce rectangular columns and different size square columns. In the embodiment shown in FIG. 1, the smaller columns 15 are designed to ultimately form micro-needles, while the wider rectangular columns 17 and larger square columns 19 can be present to control etching uniformity and/or provide mechanical protection to the smaller features. Similarly, spacing can be varied to achieve open areas between arrays and/or provide for other non-array type features, e.g. contacts, supports, insertion stops, etc. Further, in some embodiments of the present invention, more than one set of saw cuts can be used. For example, three sets of saw cuts at 60 degrees relative to each other can be performed to form triangular- or hexagonal-shaped columns.

The wafer can be etched to reshape the vertically-extending columns under conditions suitable to produce a plurality of substantially uniformly shaped needles from the vertically-extending columns. For example, etching can be performed using a dynamic etch to round the columns and a static etch to form points at the tips of the columns. In dynamic etching, the width of the columns are isotropically thinned. During the dynamic etching process the wafer can be mounted in the Teflon wafer holder, and immersed with columns facing down, into an acid mixture of HF—HNO₃. Typically, the HF—HNO3 ratio is about 1:19, although other proportions can be suitable. The wafer holder is rotated clockwise while the magnetic stirrer, rotating counter-clockwise, stirs the acid aggressively. The unique combination of wafer and stir-bar rotation help in achieving uniform etching across the high aspect ratio columns. Stirring the etchant causes an aggressive and continuous flow of the etchant into the dicing kerfs, thereby leading uniformly etched square columns with rounded corners. Suitable etching solutions can include, but are not limited to, mixtures of hydrofluoric acid and nitric acid, TMAH, or any other etchant suitable for controlled etching of the material forming the columns.

Dynamic etching can be performed by placing the wafer into or onto a suitable holder. The wafer can then be exposed to or immersed in an etching solution. The holder can be constructed of a material which is resistant to the etching solution, such as polytetrafluoroethylene (e.g. Teflon®) or other polymers. Conventional vacuum chuck wafer spinners can be particularly useful for this purpose. The wafer can be fully immersed in the etching solution and rotated in one direction. A stirrer stirs the etching solution in an opposite direction to provide aggressive and continuous flow of fresh etching solution into the dicing kerfs. During dynamic etching, the exposed columns are etched into a needle shape.

In static etching, the tips of the electrodes are preferentially sharpened over the needle trunk and the base. During the static etching process the holder is placed in the acid mixture with the columns facing upwards, and neither the acid is stirred nor is the wafer rotated. The static etch preferentially etches and sharpens the tops of the columns, until the final column shape has a sharp tip. The etch rate is greater at the tops of the columns because the activity of the etching solution at the base of microneedle is reduced, and little fluid motion is present to replenish depleted etchant.

Additional processing steps can be performed to deposit electrically conductive material onto the needles to provide a low impedance electrical connection from the needle body to the tissue in which the needle array is inserted. In one aspect, a coating can be deposited on the needle body. The coating may be, for example, one or more metals, designed to adhere to the needle body and provide an Ohmic contact between the metal and the needle body. The coating can help to provide a stable interface when inserted in vivo.

For example, for silicon micro-needles, a metal stack of iridium or platinum over titanium has proven to provide good performance for stimulation and recording. More specifically, in one specific example of this coating scheme, about 50 nanometers of titanium, following by about 240 nanometers of platinum, or about 100 nanometers of iridium were deposited by sputtering. The titanium provides an adhesion layer to the silicon needle body. After conversion to iridium oxide, the iridium layer provides a stable low-impedance electric interface when inserted in vivo. Iridium can be converted to iridium oxide by electrochemical activation. Other coatings can also be used, including for example combinations of titanium and iridium, platinum and iridium, or even direct sputtering in oxygen plasma of iridium oxide directly onto the silicon needle tips.

Other optional aspects can include forming electrical contacts on the back side of the needle array for facilitating electrical connection to other features and/or components which allow the needles to be individually addressable.

Coating of the tips of the needles with electrically conductive material may be facilitated by masking the shafts of the needles. In one aspect of the present invention, the needles are submerged in a resist material so that they are at least partially embedded within the resist material. Thus in one aspect, the needles may be entirely embedded within the resist material. Alternatively, the needles can be embedded to a limited depth of resist material, so that the tips of the needles are exposed at a desired length. The exposed tip length can then be made to constitute the active area of the electrodes by metallizing them, while the length of shaft embedded in the resist material is left unaffected.

An exemplary process flow for masking and metallization of needle tips is shown in FIGS. 2A through 2E. FIG. 2A shows a wafer 20 having a plurality of needles 22 etched thereon. A glass insulating material 24 electrically isolates each of the needles in the array while metal contacts 26 provide conductive contacts for device integration. During the photolithography process only the tips are exposed (no resist on tips) such that the rest of the electrode array is immersed in photoresist. FIG. 2B illustrates coating the wafer in resist material 28. An upper portion of the resist material can be exposed to UV and developed such that the resist material is selectively removed around the needle tips 30 as shown in FIG. 2C. A conductive metal 32 can then be deposited over the wafer as shown in FIG. 2D. Deposited metal will cover substantially all surfaces such that on the needle tips the metal is in direct contact with silicon whereas in other areas it is in contact with photoresist. Upon exposure to a resist solvent (e.g. acetone), the resist will dissolve and the metal will lift-off from the rest of the electrode array, except the tips. As such, the metal will be substantially only coated on the tips of the electrodes. The tip exposure area (e.g. coated tip depth) during tip metallization can be controlled by spinning speed during resist coating and ultraviolet (UV) exposure time. The use of resist materials in metallization is also described further in related U.S. patent application Ser. No. 11/807,763. FIG. 3 is an SEM micrograph of a UEA showing metallized tips using the above described process. The metalized tips are lighter and are substantially uniform in tip exposure area.

The size of the active area of the electrode has a significant impact on electrode performance, so it may be desired to carefully control the depth of resist and, effectively, the exposed tip length. The resist material may be spin coated onto the wafer using relatively low revolution rates of about 20-500 rpm, and often from 50 or 100-500 revolutions per minute (rpm) as compared to conventional spin rates of 2000-3000 rpm used in semiconductor device fabrication. The spin rate should be sufficiently low to embed the structures in the resist while also providing a sufficiently uniform coverage of resist material across the wafer. In a particular embodiment, the depth of resist is controlled by varying the spinning speed during resist coating. As shown in FIG. 4, increased spinning speed results in increased tip exposure. This allows for processing of three-dimensional and highly non-planar profiled surfaces unlike conventional photolithography processing of relatively flat and stepped features. As a result, this approach allows for a more simplified process, in that a substantially reduced amount of materials are needed in fabrication. Furthermore, this approach has been found to result in more uniform depth of resist and therefore more uniform exposed tip lengths.

Another advantage of the above described techniques is that the upper portions of the high-aspect ratio structures need not be planar. For example, as described in U.S. patent application Ser. No. 11/807,766, incorporated here by reference, a micro-needle array can have micro-needle tips disposed in a non-planar surface, e.g. trough, saddle, cylindrical, or slant arrays. It has been observed that surface tension of the resist material helps the upper surface of the resist material to conform to nearly any curvature of the top of the high-aspect ratio structures. After application, the resist material can be cured, for example by baking. Before curing, the wafer may be optionally placed under vacuum (e.g., pressure less than about 10⁻² torr) to encourage bubble elimination from the resist material. In one alternative aspect, the vertically-extending columns at the periphery of the wafer can be configured to define a well of sufficient depth to contain the resist material without the need for an additional container. The resist material can alternatively be removed via laser ablation.

Once the desired needle array device is formed, the needle array may be encapsulated in a non-conductive, non-reactive material to help improve compatibility in vivo. For example, materials can include parylene-C, silicon carbide, and/or silicone. Parylene-C can, for example, be deposited by low-pressure chemical vapor deposition. It will be appreciated that the tips can be left unencapsulated to allow electric contact between the micro-needles and the tissue into which the array is inserted. For example, the tips may be masked prior to the encapsulation. Alternately, the entire needles may be encapsulated, and then the non-conductive, non-reactive material removed from the tip portions.

In order to decrease the impedance of their active areas the electrode tips need to be de-encapsulated. This process can also be carried out on a wafer scale. However, when the needles are encapsulated while part of an intact wafer, once the arrays are cut from the wafer exposed edges are created. For improved biocompatibility, each needle array should be completely covered with the encapsulating layer. Therefore, the arrays can be singulated prior to depositing of the encapsulating layer. Previously this would hinder realization of the benefits of wafer scale fabrication, at least for the steps of encapsulation and de-encapsulation. In view of this limitation, the present invention provides a method in which the wafer is mounted on a second (carrier) wafer, e.g. by using a wafer grip. Then singulation can be done with a thick blade, EDM, or other material removal process to singulate the arrays in the product wafer, while leaving the carrier wafer intact. In this manner, individual arrays remain in position with respect to one another without becoming multiple loose arrays.

One suitable fabrication process is shown in the diagrams of FIGS. 4A through 4N. FIG. 5A shows a silicon wafer 50 in which a plurality of trenches 52 are cut on the wafer back-side 54 as shown in FIG. 5B. These shallow trenches are then filled with a suitable electrically insulating material 56 such as glass. The shallow trenches generally form a grid which ultimately electrically isolates individual needles in the array when the needles are cut and then etched from the opposite front-side of the wafer. FIG. 5D shows where individual needle bases are metalized with electrical contacts 58 on the back-side in areas of the silicon surrounded by the insulating material. A plurality of deeper trenches 60 is then cut into the front-side 62 of the wafer 50 (as previously described) and shown in FIG. 5E to form an array of extended columns. The columns are then etched to form the arrays of needles 64 as shown in FIG. 5F. FIG. 5G shows the wafer after tip metallization as previously discussed where tips 66 of the needles are coated with a desired metal or combination of metal layers. A carrier wafer 68 can be mounted to the back-side of the wafer as shown in FIG. 5H. The carrier substrate or wafer can be a rigid sacrificial substrate or a rigid substrate which is left in place as part of the final product. The individual arrays can then be singulated without breaking or singulating the carrier wafer. In this manner edges 70 of each array are now exposed. In FIG. 5J a parylene coating 72 (or other protective coating) can be deposited over the entire wafer. The thickness of this protective coating can be varied based on the desired performance, type of material, and the like.

In order to retain electrical conductivity of the metalized tips it then becomes desirable to remove the protective coating over the tips. Thus, a resist etching approach can be followed similar to that used to deposit the metal on the tips. Alternatively, the protective coating can be deposited everywhere except the tips, e.g. by masking or selective directed deposition. FIG. 5J shows a wafer where the entire wafer assembly is again coated in a suitable resist 74. An upper portion of the resist can be removed as previously discussed to expose the metalized tips which have the protective coating thereon. As shown in FIG. 5K the protective coating can be removed from the tips via a suitable etching process such as oxygen plasma etching or the like. This way the metalized tips are once again exposed while the remainder of the wafer is encapsulated in a protective coating. The amount of etching time determines the amount of exposure of the tips and removal of the coating. Thus, in this embodiment, the tips are de-encapsulated during the same step as removal of the resist material. Various ways of removing the encapsulation from the tips can be used. For example, reactive ion etching using inductively coupled oxygen plasma can be performed. The oxygen plasma etching removes the resist material starting at the tips, and as the tips are exposed, removes the electrically insulative coating as well. The resist material can then be removed to form the needle arrays on the wafer as shown in FIG. 5L.

Individual arrays can be recovered either by removing the carrier wafer or by cutting through the carrier wafer along gaps 76 formed around the array perimeter edges. Individual arrays 78 (shown in FIG. 5M) can then be used or further integrated into a final device. When wafer-scale fabrication steps are completed, the wafer can be separated into a plurality of individual needle arrays such as by conventional dicing or other techniques. In embodiments where separated arrays are carried on a carrier wafer, the arrays may be removed from the carrier wafer. Once separated, additional fabrication steps may be performed on the individual needle arrays, such as flip chip mounting of an integrated circuit to the needle array. Optionally, these additional fabrication steps can be performed while the arrays are still associated on the carrier wafer. In this manner, at least some of the fabrication steps can be streamlined and performed simultaneously across the wafer. In most cases, this may involve performing various deposition and/or photolithographic steps to the backside of the wafer.

As an illustration of one alternative, the tips of the needles may be de-encapsulated using laser ablation (e.g., using an excimer laser) and shadow masking techniques. For example, a shadow mask can be made by forming holes in a wafer in positions corresponding to the needles. The holes may be etched, for example using an anisotropic etchant (e.g. KOH or TMAH) or by deep reactive ion etching. The array can then be temporarily joined to the shadow mask and the needles can be inserted through the holes. The thickness of the shadow mask is equal to the height of the electrodes minus the desired exposure height of de-encapsulation. FIG. 6 is an SEM micrograph of tip de-insulation using foil masking having a relatively high non-uniformity. FIG. 7 is an SEM micrograph showing de-insulated tips in accordance with an embodiment of the present invention having a high tip length uniformity.

The principles of the present invention can be readily extended to production of arrays having highly irregular backside geometry. For example, wireless communication, power coils and other devices can be integrated onto the backside of the array. However, such features also involve significantly irregular and non-planar geometry which introduces some complications into processing. FIGS. 8A-8I illustrate flow process schematics applying the above methods to such devices. Conventional array-level manufacturing does not allow some of the processes of system integration, such as flip chip bonding, assembly of functional components, under-filler treatment and the like, to be carried out on a wafer scale. Owing to the unique configuration of the integrated wireless array post-assembly processes, the back side is highly non-planar (e.g. coil mounted on the IC). As a result of this non-planar topography, performing parylene deposition and de-insulation processes on these architectures with current techniques is challenging.

FIG. 8 (A-G) demonstrates a process flow for fabricating a wireless UEA. The process steps up to that shown and discussed in connection with FIG. 5L are common to the process flow for a wireless array. In order to pursue flip-chip bonding on a wafer scale, incomplete edge arrays of the wafer and non-needle fins can be trimmed as illustrated in FIG. 8A. It is recalled that the non-needle fins have now served their primary purpose of controlling etch rates and contours of the needles for increased uniformity of the needles. The wafer 80 can then be mounted on a customized carrier wafer or holder 82 with the back-side 84 of the wafer facing outward as in FIG. 8B. The holder can include supports 86 in between arrays in order to support the wafer during processing. This can also protect the tips of the electrode array during flip chip bonding. FIG. 8C illustrates various IC and other features onto the back-side of the arrays. Although other features can be formed, FIG. 8C shows a fully assembled device with functional components like the integrated circuits chip 90, Surface Mount Devices (SMD) components 92, coil 94 integrated on the back plane of each individual UEAs. Further, an electrically conducting spacer 96 can electrically connect the IC chip with the coil.

The array assemblies can then be release from the holder and the same or similar holder 88 can be removably secured to the back-side of the wafer as shown in FIG. 8D. The wafer is typically flipped so the arrays can then be de-insulated (i.e remove parylene from the tips of the electrodes to facilitate charge transfer to the neural tissue) on a wafer scale. The processed arrays can then be singulated to form individual singulated IC chips, along with the functional components, as shown in FIG. 8E. Owing to non-uniform topography of the back side because of the assembly processes (coil, IC, SMD components), the wafer can be mounted on a customized carrier wafer/holder for singulation. Parylene can be deposited on the assembled devices in a process similar to that previously described. For example, the parylene can be deposited in two steps: first, on electrode side and then on back-side. In order to de-insulate the electrodes a photoresist can be used as a masking layer. Since the back-side of the device needs to be protected, the assembled device can be mounted on a customized Teflon holder 88 as shown in FIG. 8F. As before, the tip exposure can be controlled by the spin speed. As the photoresist is etched in the oxygen plasma the parylene also gets etched. FIG. 8G shows an electrode device after de-insulation. This process flow allows transferring several manufacturing steps to wafer-scale processing, which not only improves yield and reproducibility of the wireless array but also allows many processing steps associated with system integration of the wireless arrays (like flip-chip bonding, under-filler treatment etc.) to be performed on a wafer scale.

While the forgoing exemplary embodiments are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the invention. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below. 

1. A method for wafer-scale fabrication of needle arrays comprising: (a) providing a wafer having an upper surface and a lower surface; (b) mechanically modifying the upper surface to produce a plurality of vertically-extending columns; (c) etching the wafer to produce a plurality of needles from the plurality of vertically-extending columns; (d) coating tips of the plurality of needles with an electrically conductive coating; (e) securing a carrier substrate to the lower surface of the wafer; (d) separating the wafer into a plurality of individual needle arrays, each having at least one edge, while leaving the carrier substrate intact; (g) encapsulating the individual needle arrays with an electrically insulative coating so that each edge is covered by the electrically insulative coating; and (h) de-encapsulating the tips of the plurality of needles.
 2. The method of claim 1, wherein etching the wafer includes a first dynamic etching to form rounded columns, followed by static etching to form the plurality of needles having sharpened tips.
 3. The method of claim 2, wherein etching the wafer comprises the steps: (a) placing the wafer on a vacuum holder; and (b) spinning the wafer while in contact with an etching solution.
 4. The method of claim 3, wherein before coating, the plurality of needles are encompassed in a resist material to a depth that exposes the tip of each needle to a predetermined tip length to be coated with the electrically conductive coating.
 5. The method of claim 4, further comprising placing the wafer in a vacuum to encourage bubble elimination from the resist material prior to curing of the resist material.
 6. The method of claim 4, wherein the resist material is applied by spin coating at a low spin speed.
 7. The method of claim 6, wherein the depth is controlled by controlling the spin speed.
 8. The method of claim 7, wherein the spin speed is from about 20 rpm to about 500 rpm.
 9. The method of claim 4, wherein the tip length is substantially uniform across needles.
 10. The method of claim 9, wherein a degree of tip length uniformity is within about 50% of the tip length.
 11. The method of claim 4, further comprising stripping the resist material from the needles after coating.
 12. The method of claim 4, wherein the tips of the plurality of needles define a non-planar surface to which a top layer of the resist material conforms.
 13. The method of claim 1, wherein de-encapsulating the tips of the plurality of needles comprises: (a) encompassing the needles in a resist material leaving the tips exposed to a predetermined tip length; and (b) applying a further processing step to remove the electrically insulative coating from the tips.
 14. The method of claim 13, wherein the further processing step is oxygen plasma etching.
 15. The method of claim 13, wherein the further processing is laser ablation.
 16. The method of claim 1, wherein mechanically modifying includes: (a) forming channels in the lower surface to form a grid of electrode bases; (b) filling the channels with an electrically insulating material to form an electrically insulating network; and (c) forming a complimentary set of channels on the upper surface opposite the channels in the lower surface to form the plurality of vertically-extending columns.
 17. The method of claim 16, wherein the electrically insulating material is epoxy or glass.
 18. The method of claim 16, further comprising forming metal contacts on each of the electrode bases, said metal contacts being electrically isolated from one another.
 19. The method of claim 16, wherein the channels in the lower surface and the complimentary set of channels are formed by wire EDM or dicing.
 20. The method of claim 1, wherein the second wafer is removed subsequent to de-encapsulating the tips.
 21. The method of claim 1, wherein the carrier substrate is left in place. 